Effectiveness of Multilayer Ceramic Capacitors for Electrostatic Discharge Protection - In Compliance Magazine

By mounting multilayer ceramic capacitors (MLCC) on the PCB I/O connector pins that are the entry point for ESD, a simple technique for handling ESD can be realized. EMC engineers recommend using 0603 MLCC near each connector pin to enforce low-inductance mounting strategies related to PCB traces and vias. When providing ESD protection for I/O pins, when choosing a surface mount technology (SMT) MLCC, the engineer will specify the ESD capacitor value, its DC voltage rating, and the technology choice (X7R or C0G). MLCC is used as an ESD bypass or parallel device to transfer ESD current to the ground. ESD protection devices should implement ESD mitigation measures and should not exhibit degradation, while maintaining ESD robustness throughout the life of the product. However, post-ESD inspection of the small footprint 0603 MLCC showed severe structural damage, and showed a huge change in its impedance characteristics electrically. This is very different from pre-ESD capacitors, which leads to excessive low-frequency leakage and malfunctions.

Electrostatic discharge (ESD) is one of the most important reliability issues in the electronic circuit industry. Generally, in the integrated circuit (IC) industry, one-third to half of all field failures (customer returns) are caused by ESD. As the susceptibility of smaller circuit elements to ESD damage becomes more and more common in new technologies, the work of understanding ESD failures through modeling and analysis has increased accordingly. Integrated circuit manufacturers provide ESD test information. However, ESD data related to IC-level standards (Human Body Model (HBM), Charging Device Model (CDM), Machine Model (MM) and Latch-to-System Test) are often confusing.

The design of robust ESD circuits is still challenging, because as the size of critical circuits continues to shrink, ESD failure mechanisms become more acute. Circuit board designers are further limited by their ability to design highly crowded PCBs and meet ESD requirements. HBM provides a lot of insights into equipment behavior during ESD events [1,2].

An ESD event is the transfer of energy between two objects at different electrostatic potentials through contact or through an ionized environmental discharge (spark). This transmission has been modeled in various standard circuit models to test the compliance of equipment targets. These models typically use capacitors charged to a given voltage, and then use some form of current limiting resistor (or ambient air conditions) to deliver pulses of energy to the target.

In order to meet the module-level ESD test, various methods and techniques have been implemented and studied on printed circuit boards. An effective technique is to add discrete noise decoupling components or filters to complex CMOS-based IC products to decouple, bypass or absorb transient voltage (energy) during system-level ESD testing [3]. Various types of noise filter networks can be used to improve system-level ESD stress testing, including capacitor filters, ferrite beads, transient voltage suppressors (TVS), metal oxide varistors (MOV) and 2nd order LC filter or 3rd order π-section filter.

Multilayer ceramic capacitors (MLCC) are used as an ESD bypass mechanism at the connector pins of electronic control modules. Automotive control modules may require the use of a single high-density connector with a pin density exceeding 200. In a typical application, the connector may provide designers with a 4 x 50 matrix (4 rows per row, 50 pins per row) in crowded PCB real estate. In order to provide ESD protection for each I/O pin on highly congested PCB real estate connectors, design engineers recommend the use of 0603 type MLC capacitors. In most applications, MLC capacitors used for ESD protection are rated at 100V. However, the post-ESD characteristics of MLCCs are often ignored or misunderstood. In fact, the characteristic impedance behavior of MLCC exposed to ESD stress has changed dramatically. A close inspection of the MLCC will reveal permanent structural damage, resulting in excessive low frequency leakage. The post-ESD behavior of MLCC will cause the functional deviation of the control module. Fundamentally speaking, it is unsafe to use the product in its intended application. As stated in this article, it is recommended not to use thin 0603 capacitors for ESD protection. Alternative solutions can be met by using a thin transient voltage suppressor (TVS) or fast metal oxide varistor (MOV). However, the 0805 type MLCC with high value capacitance (> 47 nF) provides a good solution and can be safely used as an ESD bypass component.

MLCC used as a protection device or mechanism should regard voltage, peak power and energy as key components of ESD threats. Therefore, the amplitude and timing of ESD components must be fully characterized. Therefore, the protection structure should reduce the voltage, peak power and energy threats by shunting the stress current from the fragile parts of the microcontroller and other ICs [4].

In order to solve the ESD problem, the MLC capacitor used as an ESD bypass or filter component on a printed circuit board (PCB) must safely ground the ESD transient current. It is important that the MLC capacitor used as a bypass component must safely absorb ESD voltage and current and protect the device under test from degradation. In addition, MLC capacitors must remain within their parameter tolerances in order to be considered a reliable protection mechanism.

Multilayer ceramic capacitors are designed for applications that require smaller physical size, larger capacitance, and higher insulation resistance. Type II general purpose 0603 (1.6 mm x 0.5 mm) X7R type (-55°C to +125°C) is a common choice for automotive electronic control module design. Therefore, the usual practice is to use X7R MLCC as an ESD protection component on all I/O pins.

Figure 1 shows the horizontal grinding of 0603 MLCC (magnification X 100) with a plate spacing of 21 nmm for 10 nF X7R type II capacitors. The designed high-value capacitor has an increased number of plates. This will result in a narrow dielectric thickness, which may be a disadvantage of high voltage transients. Currently (May 2012), the capacitor value of the II X7R 0603 type (100 V) is between 180 pF and 39 nF maximum. However, the value range of capacitors with the same technology but with a larger physical size (0805) varies from 220 pF to a maximum of 120 nF. If it is determined that the value of the ESD protection capacitor exceeds the maximum value of 39 nF available in the 0603 package, this may be an important factor.

Figure 2 illustrates two different styles of MLCC technology for conductive plate design. Capacitor manufacturers recognize the problem of overvoltage stress and provide ESD enhanced MLCC products. A close inspection of Figure 2 shows that the Type B MLCC is an ESD enhanced design.

Figure 3 illustrates the horizontal grinding of an ESD enhanced MLCC at x100 magnification. The comparison with Fig. 1 proves the difference in board geometry design.

A printed circuit board designer with basic EMC training is required to determine the best installation strategy for ESD capacitors. EMC engineers verified the "Y connection" topology of all ESD capacitors on each I/O pin of the connector. The MLCC must be placed close to the I/O pins (<1cm) and short traces (<1cm) on the PCB return plane. In this way, the increased PCB parasitic trace inductance and its impact on the efficiency of the ESD bypass capacitor can be minimized. The usual consideration is to limit the additional inductance caused by the PCB mounting inductance, thereby providing a low impedance path for the ESD current to flow back to the return plane.

Another limitation is to use the lowest value capacitor available, which is most effective at higher frequencies. ESD can cause the bandwidth of the RF current to exceed 330 MHz. The choice between 1 nF and 680 pF can easily be reduced to the latter. However, the ESD HBM consists of a capacitance of 150 pF, so it is better to use a higher value MLC capacitor. By combining HBM capacitors and MLCCs, a voltage divider network is established. As shown in Equation 1, the voltage generated on a larger MLCC will reduce the voltage generated on the integrated circuit.

      Equation 1

Therefore, where V

<< V

, Request C

>> C

.

Several electrical models of capacitors are provided in textbooks and RF publications used by the EMC/RF community to describe the electrical performance of MLC capacitors. A simple tandem RLC network is usually used to provide accurate behavior for most applications. However, simple RLC models cannot provide other technical insights required for analysis of MLCC exposure to ESD pulses. The modified model shown in Figure 1 has other elements to describe the performance of MLC capacitors subjected to ESD stress. In fact, the model described here is an accurate electrical description, which is necessary to consider various physical properties within the capacitor.

Figure 5 shows the impedance characteristics of 680 pF and 10 nF Type II (0603, X7R MLC) capacitors.

ESD is a high-frequency pulse with a rise time of less than one nanosecond, resulting in a spectral content exceeding 330 MHz. Therefore, as shown in Figure 2, the choice of ESD capacitors is reduced to a smaller MLCC value. A closer inspection of Figure 2 reveals that 680 pF (1.71Ω at f = 330 MHz) has a lower impedance compared to 10 nF (3.97). f = Ω at 330 MHz). Another consideration may be the result of the capacitive load of certain I/O signals (such as the CAN bus), where a limited amount of capacitance can be added to the communication bus.

As mentioned in the previous paragraph, the requirement for low-value ESD capacitors may suggest the lowest value MLCC available in the industry. In addition, the third factor is listed in Table 1. R3 (insulation resistance) may increase the motivation to use the lowest value MLCC. However, further insight is needed to distinguish the obvious and simple options.

In Table 1, all the nominal and parasitic components of the two capacitors are listed according to MLCC supplier A.

It is important to note that for smaller value capacitors, the value of the insulation resistance R3 is an order of magnitude higher (Table 1). As more boards are stacked in the same physical volume of the 0603 package to accommodate higher capacitance values, the dielectric thickness will be reduced by 14.7 times. Therefore, since the dielectric material between the capacitor plates is thinner, the insulation resistance of high-value capacitors will be reduced by the same ratio (capacitor ratio: 10 nF / 680 pF = 14.7, insulation resistance ratio: 0.1 x 10

Ω/ 14.7 x 10

 Ω = 1/147. Obviously, a higher value capacitor will withstand dielectric breakdown at a lower ESD voltage. This argument shows that for ESD applications, only low-value capacitors with higher insulation resistance need to be considered to prevent dielectric breakdown, which is 680 pF vs. 10 nF. Further investigation is needed to resolve the accuracy of the above statement.

If the smaller capacitor has a higher insulation resistance (as shown above), it is important to check the insulation resistance behavior after the ESD test. For further understanding, it is important to evaluate the impact of ESD stress on 680 pF and 10 nF capacitors through the characteristic impedance of the capacitor after ESD.

ESD testing for automotive applications is based on a human body model specified by an original equipment manufacturer (OEM) [5,6,7,8,9].

A typical HBM discharge network consists of a 150 pF capacitor and a 2 kΩ resistor. HBM capacitors can be charged to 25 kV for air discharge testing. The static charge accumulated on the 150 pF discharge network capacitor (charged to 25 kV) totals 3.75μC. ESD is a high frequency, high voltage and high current event that can deposit 46.875 mJ of energy in the protection device in a relatively short time.

HBM can gain insight into device behavior during ESD events. Although HBM stress is characterized by a certain charging voltage V

, The 2kΩ series resistance of the circuit is usually much larger than the impedance of the device under test, so we regard the HBM tester as a current source, and the peak HBM current is equal to 12.5A. (V

= 25 kV, air discharge).

In order to evaluate the impact of ESD stress on 0603 MLCC, two different types of tests were performed. Since the assembled electronic control module is the purpose of actual testing, it is very important to evaluate the impact of ESD stress in accordance with OEM ESD testing technology. In another method, a 0603 MLCC network is prepared, as shown in Figure 6, with two short lines (<1 cm) at each end. Terminal 1 is connected to the ground plane, and is usually connected to the return lead of the ESD spray gun. Slowly approach the ESD discharge tip to the floating terminal until air discharge is achieved.

The Agilent 4294A impedance analyzer (40 Hz-110 MHz) was used to record the before and after ESD characteristics of the 0603 capacitor with the help of the Agilent 16034G test fixture.

Remove the capacitor from the test PCB or ESD network wire and install it inside the 16034G test fixture for impedance characterization.

Decided to design in accordance with strict EMC guidelines and apply ESD pulses to the fully installed automotive electronic control module. Since OEM ESD requirements provide guidelines for remote I/O access ESD stress testing [7,8,9]. The HBM model with discharge network outlined in Section IV was calibrated, and ESD voltages of +/- 4 kV to +/- 25 kV were applied sequentially. After each discharge, follow the previous method to remove the MLCC and analyze it on the impedance analyzer.

Figure 7 illustrates the effect of an ESD pulse with a 680 pF capacitor at +/- 15kV level.

Figure 8 illustrates the effect of an ESD pulse with a 10 nF capacitor at +/- 15kV level.

The dielectric damage of the capacitor after ESD is shown at a magnification of 100 in Figures 9 to 11 (horizontal grinding). The figure shows the physical damage to X7R and COG technology.

In Figure 12, the modified electrical model shown in Figure 4 is used to illustrate the effect of ESD on the two capacitors. In the electrical model in Table 1, R3 is replaced by a 500Ω resistor to represent the nominal value before ESD provided by the MLCC manufacturer in Table 1 (14.7 x 10

 Ω).

It is important to note that a 10 nF capacitor produces severe leakage in the 40 Hz to 20 kHz range, while for 680 pF, the higher frequency is about 200 kHz. The impedance of the two capacitors has a resistance value of 500Ω recorded in the above frequency range. Therefore, it is concluded that ESD has caused irreversible and permanent damage to MLCC. The behavior after ESD shows that due to the metalization of the capacitor plates, physical damage will be caused to the dielectric material. Referring to Figure 4, it is clear that R3 has shifted from the pre-ESD nominal value in Table 1 (for 680 pF, R3 = 1.471 x 10

Ω, or for 10 nF, R3 = 0.1 x 10

Very low values ​​from Ω to 500Ω).

The reason why 680 pF MLCC has 500Ω leakage at frequencies up to 200 kHz, while 10 nF only shows adverse effects at frequencies up to 20 kHz, can be explained as follows: The circuit in Figure 4 is simplified as a parallel connection of C1 and C1. When R3 is at low frequency, the inflection point of the impedance curve appears at f~1 /2πR

C

. After ESD, the MLCC of 680 pF is dominated by R3 from DC to ~300 kHz, while R3 only contributes up to 20 kHz to the 10 nF capacitor. Figure 13 illustrates the drop in leakage resistance after ESD.

Obviously, a smaller size MLCC will suffer from great leakage in a higher frequency range. Contrary to previous recommendations, it is recommended to use a higher value MLCC.

As an extension of exposing 0603 MLC capacitors to ESD stress, additional ESD tests were performed on modules with larger 0805 MLC capacitors. Figure 14 illustrates the effect of +/- 25 kV HBM ESD stress on a 4.7 nF capacitor. Obviously, a 4.7nF 0805 capacitor will not meet ESD requirements. However, expanding the size (value) of the capacitor in the 0805 package to 10 nF will result in ESD compliance.

This study is an examination of the physical damage of 0603 MLC capacitors exposed to ESD transients. It shows that ESD voltage exceeding 15 kV can cause permanent damage to dielectric materials. It is not recommended to use 0603 MLC capacitors for I/O connector pins, as ESD bypass mechanisms should be avoided. However, if the capacitor size exceeds 10 nF and the rated voltage is 100 V, in a larger package, the 0805 MLCC will meet the ESD stress of 25 kV. The preferred ESD bypass solution will use a low capacitance transient voltage suppressor (TVS, C

<100 pF) or fast metal oxide varistor (MOV).

However, I/O pin ESD capacitors in the range of 1 nF to 100 nF are usually used as input RF filters on the connector pins. The ESD capacitor provides a bypass element for the RF current induced on the module harness due to the impact electromagnetic field. Low-value TVS capacitors are not sufficient to provide the required filter in a frequency bandwidth of 1 MHz-200 MHz. It is recommended to use TVS in parallel with 0603 capacitors (10 nF-100 nF) when allowed.

IEEE Senior Member

EMC senior technical expert,

Robert Bosch LLC, Plymouth, Michigan, USA

IEEE Fellow

Politecnico di Torino

IEEE member

Shabestar, Iran, Department of Electrical Engineering, Azad University

School of Electrical and Computer Engineering, Tehran University

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