Die-To-Die Stress Becomes A Major Issue

Advanced nodes and packaging turn small problems into big problems.

When identifying and planning in advanced nodes and advanced packages, pressure becomes more and more important, because simple mismatches can affect the performance, power consumption and reliability of the device throughout its expected lifetime.

In the past, the chip, package, and circuit board in the system were usually designed separately and connected through the die-to-package and from the package to the circuit board interface. However, now there are so many connections and possible interactions that it is no longer impossible to work in isolation. These are potential sources of stress, and they may increase as designs become more integrated and complex.

"3D-IC chip packaging system and multiphysics director and product expert Sooyong Kim said: "There are no longer hundreds of connections in the interface. "

. "Nowadays, there are millions of collision connections from one mold to another. And the materials used may come from different foundries and different packaging groups, bringing a variety of heterogeneous inputs into the picture in."

Pressure has added a whole new level of complexity to this equation and forced some fundamental changes in the chain of responsibility. "This used to be the job of an off-chip engineer," Jin said. "Now, this is the job of a chip engineer. Many parts are silicified, so because of these tight integrations, different methods are needed to analyze mechanical problems. These tight integrations also affect performance and tend to increase heat. Initially. , This is an electrical problem. Then, it becomes a thermal problem. Now it is a mechanical problem. However, in a complex multiphysics cycle, this mechanical problem affects the electrical problem, thereby affecting the heat inside the chip, etc. Wait."

Strain and stress belong to the law of elasticity or Hooke's law, which states that for relatively small object deformations (such as semiconductor devices), the displacement or magnitude of the deformation is proportional to the deformation force or deformation. Under these conditions, after the load is removed, the object will return to its original shape and size.

"About ten years ago, when we talked about the pressure inside integrated circuits, people would come up with the concept of strained silicon," explained CT Kao, a solution architect at the Digital & Signoff Group.

. The strained silicon inside the transistor pulls the silicon atoms apart. The silicon layer is on the silicon germanium layer, and when silicon is deposited on top of the silicon germanium, these atoms are pushed away. This increases the electrical mobility, brings good results, and reduces some obstacles. In this way, the stress is caused by machinery, heat and force. "

At early stages

, These effects can be largely controlled by design rules. The size of the transistor is large enough that by controlling the spacing and enclosure between the active region and the well region, the effect can be neglected. Now, with semiconductor design and single-digit nanometer manufacturing, these effects are showing up in ways that are not so easy to avoid. When stress is applied to transistors, they change the mobility of carriers, thereby changing electrical properties. These stresses usually take the form of a mid-range geometric configuration within the chip.

"With the end of Dennard scaling technology, foundries continue to look for ways to improve transistor performance," Yves Laplanche, Distinguished Engineer in the Physical Design Group

note. "The use of mobility enhancement technologies based on pressure engineering has been widely used. These technologies are either directly focused on the channel and source/drain materials, such as using germanium to change the lattice structure, or involving specific process steps. The process step will stress the transistor from its surrounding environment. This is the case with stress memory technology (SMT) or the selection of a specific contact edge stop layer (CESL). In these cases, the stressing device environment will greatly affect these technologies For example, NMOS and PMOS can have opposite behaviors. With FinFET technology and the small geometries in the 7nm and 5nm nodes, the relative influence range of changes will increase."

For example, the distance between the transistor and the edge of the well can cause stress, which can lead to erroneous electrical simulations. These layout issues not only affect chip-level design, but even affect

Block level.

"For example, consider a chip in which IP blocks are placed multiple times. When the simulation is performed in standalone mode, the IP blocks may fly through, but in the context, due to the different pressures exerted by surrounding elements, each placement will produce different Behavior. Another example is an analog block, whose symmetrical matching is essential for correct performance. Independent circuits may behave as an ideal symmetrical state, but in context, a component may be subjected to different stresses from its mirrored twin, thereby destroying Expected symmetrical behavior,” explains John Ferguson, Calibre DRC Application Product Marketing Director.

.

In fact, in the development stage of physical IP, the pressure effect is both a challenge and an opportunity. "In the memory macro or analog module, the layout and proximity of all devices can be strictly controlled. On the other side of the spectrum, in the logic library, the surrounding environment of each standard cell can be changed. Specifically, "Placement The “and wiring” tool can create an almost unlimited number of possibilities for a combination of units. In the design of Arm’s physical IP, a comprehensive analysis of the impact of pressure has been carried out and taken into account in the definition of the architecture to incorporate potential performance Changes remain within defined boundaries without compromising the area of ​​the entire system. The remaining changes will be considered in the electrical modeling of our IP design. Smart implementation choices can differentiate performance to target the power required by the market , Performance and area (PPA),” Arm’s Laplanche explained.

Certain factors are the main cause of stress. Chips are getting bigger and bigger, and they are usually packaged on wafers, such as TSMC’s silicon-on-wafer (SoW) method. Ansys’ Kim said: “If you look at its picture, the real wafer after generation, but before bonding to the die, has actually been significantly bent.” “What will you do? When this happens, The electrical properties will change. Is it completely bonded? Is it a different material? Now, it is important to understand the silicon process, and the traditional mechanical engineer does not understand the silicon process. But without knowing this, it is impossible to really carry out the appropriate analysis."

All of these will affect reliability. "If it is a SoW, it is a very power-hungry chip, and depending on the application, the requirements for the application may be very high. For example, if display processing is being performed, there may be accumulated current entering the micro bump Sub-area. Compared with the ready state of the structure, is this a sustainable heat source?

Structure? That is another problem. Can it be saved after manufacturing and when it is used in the final application? Sometimes there will be a breakdown between the two. "Jin said.

Contingency engineering adds another complexity. Strain is a stress applied to silicon to improve electron mobility. But excessive stress can cause problems, such as cracks in interconnections. Over time, these problems will increase in intensity at smaller and smaller nodes.

"When something new suddenly appears, people tend to cover it with rough approximations such as first-order effects," Victor Moroz said.

Researcher of Silicon Engineering Group. "Usually it boils down to buffering. Create another buffer in the buffer to make sure you set it to the worst case. But that means keeping some performance on the desktop. Finally, in order not to waste anything, it was refined to Including second-order effects."

The dark silicon concept may be useful here, in which case the block or transistor will be powered down until they are needed. "If you use all the transistors at the same time, it will definitely melt. You have to make the circuit lazy enough. Here, you can use the on-chip monitor to detect the temperature," Moroz said. Then, if overheating is detected, it will only slow everything down. "

Heat is another cause of stress, and with the increase in transistor density and calculation strength, this problem has been increasing, especially in

The goal of many architectures is to improve the utilization of processing elements of the chip.

Siemens’ Ferguson said: “Due to more active device switching, large chips may have local hot spots.” These hot spots change the stress curve of the entire chip. In a multi-chip world, heat dissipation is even more worrying. One die stacked on another requires a longer path to dissipate heat. When it radiates its own heat, it will add some heat to the chip below, which brings new stress to the transistor of the chip, which must be considered. "

The thermal mismatch caused by the change in the thermal expansion coefficient makes the situation more complicated. "When you heat a structure that contains several materials, different materials will expand and contract at different rates," Moroz said. "In general, compared with the dielectric of a semiconductor, metal expands as the temperature increases, and shrinks more as the temperature decreases. This is the reason for the interfacial stress in the semiconductor."

To meet this challenge, not only the temperature simulation of the chip, but also the temperature simulation of the entire package is needed. Accurately designing and characterizing the electrical performance of any given transistor requires context, including packaging, input power, and switching of the entire system. Although this is possible, it may also be impractical. Another option is to design the soft IP so that it can be used safely in almost any situation. same,

Ferguson said it must be inserted safely into various packaging.

However, this is difficult when it comes to self-heating. "If you have self-heating, your ability to travel may change, but this is negligible. Although self-heating may reduce the performance of the transistor by a few percent, its heat is not enough to change the mobility. But , It will also accelerate the aging process of transistors, such as

(Negative temperature instability) Threshold shift, due to accelerated aging, which slows down the circuit," Moroz pointed out.

Packaging is an important part of the pressure/stress discussion. When considering various packaging strategies, there are many options, starting with cheap options with poor thermal conductivity.

"Since silicon is a good heat conductor, it can dissipate heat well, but the bottleneck is the use of cheap packaging to dissipate heat to the outside," Moroz said. "In it, everything will be at the same temperature because silicon is a better heat conductor than cheap packages. In applications like mobile applications that are more like high-performance applications, you may not be able to afford to use More expensive packages. These packages will emit 10 or 20 times the heat than cheaper packages. This also changes the situation and must be considered."

The commercial tools and solutions provided by leading EDA tool providers are helping designers figure out how to solve this problem.

In addition, once packaging becomes a better heat conductor, it eliminates the bottleneck of packaging, but it also makes other things more complicated. "In particular, the temperature inside the package is not uniform. No matter where you have hot spots, it will radiate to the outside. But the internal temperature is not uniform, so you must also pay attention to this." He said.

The pressure just puts the packaging together. However, as more packaging is customized, these pressures become more difficult to identify. Therefore, detailed models need to be built, but these models will quickly expand.

"As the industry continues to develop from its long history

Modeling and expanding into the world of small chips, we get a new set of sources of stress. Through silicon vias, bumps, BGAs, and stacked devices all put greater pressure on designs," Ferguson said. Historically, packaging solutions can consider some of these stress effects, but when doing so, they don’t know the transistor’s effects. Location or expected electrical performance. This method either leads to excessive restrictions on advanced packaging, which affects the overall size or cost of the complete design, or causes the design to not function properly (due to ignoring the induced stress). Although the historical method can be used Capturing these pressures, but the computational requirements for doing so are too large to be used in designs with millions or even billions of transistors. Another method is to use a dedicated compact model that can be used in reasonable calculation times Get more accurate results within."

Although tools and solutions are still evolving to address the pressure from chip level to system level, the engineering team can now take some measures to try to prevent problems in the future.

"Previously, design engineers only performed verification after completing the build," said Ansys' Kim. "But this concept is no longer valid, because the structure is very complex from the architectural point of view, and no decision has been made in advance, and these decisions will fail. Therefore, a good method is proposed in the prototype process or the architecture process, and the completion It’s very important to run "what if" before designing."

Ferguson agreed. "The whole theme of stress impact represents a whole new level of optimization. As the industry continues to follow Moore's Law and move toward a chip-based economy, there will be an increasing need for optimization. The stress and heat of components in multiple corners must be determined. The integration tool must be able to make informed placement decisions based on these parameters. And, although the industry is actively working in multiple directions, it is clear that there is still a lot of work to be done."

The starting point is the first cause of stress. Cadence's Kao said: "Under pressure, we need to study physics, we need to study the causes of stress." When people see the wafer bend up and down, they see deformation, see strain, and then measure strain. Then, they study the condition of the chip. This is not due to pulling down the spring forcefully. This is due to the increase in temperature and the shrinkage and expansion of various materials inside the wafer at different rates. This is the cause of stress and stress. When we look at the problem, we see the result, and then we try to find the cause. Then we address the adverse effects. Inside the chip, all stresses will cause breakdown, failure or separation. In the final analysis, materials, manufacturing and EDA design tools must be integrated to solve this challenge. "

good article. I like to read. However, does CESL stand for "contact etch stop layer"? (Ie contact edge stop layer"

(Note: This name will be displayed publicly)

(This will not be displayed publicly)

The optimistic industry at the beginning of the year encountered one of the biggest challenges, but it did not become a disadvantage, but quickly became a disadvantage.

For 75 years, the backbone of computing architecture has been replaced by more efficient and less versatile computing architectures.

Continued design innovation has increased the complexity of verification and prompted more companies to actually perform verification.

The appearance and behavior of the semiconductor industry will be different this year, not just because of the pandemic.

Expert on the desk: Any chip can be reverse engineered, so what can be done to minimize damage?

New data shows that due to simulation issues, more chips are forced to resell.

The number of options is increasing, but the tools and methods have not caught up.

Huge investments in electric cars, batteries and data center chips, as 26 companies raised $2.6B.

Interconnection is becoming a limiter on advanced nodes.

Chips are encountering technical and economic obstacles, but this has hardly slowed down the development speed of design size and complexity.

As implementation evolves to maintain relevance, new technologies may surpass SerDes.

Predicting the power or energy required to run AI/ML algorithms is a complex task and requires an accurate power model, which does not exist today.

Necessary cookies are absolutely essential for the normal operation of the website. This category only contains cookies that ensure the basic functions and security features of the website. These cookies do not store any personal information.

Any cookies that are not particularly necessary for the normal operation of the website. These cookies are specifically used to collect user's personal data through analysis, advertising and other embedded content, and are called unnecessary cookies. You must obtain user consent before running these cookies on your website.