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CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory | Science Advances

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These authors contributed equally to this work.

Ferroelectric memory has been intensively studied for decades, because compared with conventional flash memory, ferroelectric memory has higher speed, lower power consumption and longer service life. Although great efforts have been made to develop ferroelectric memory based on perovskite oxide on silicon, the formation of an undesirable interface layer substantially impairs the performance of the ferroelectric memory. In addition, due to the high processing temperature, non-CMOS compatibility, difficulty in scaling and the complex composition of perovskite oxides, three-dimensional (3D) integration is unimaginable. Here, we show a unique strategy that can solve key problems by applying oxide-based ferroelectrics and oxide semiconductors. Therefore, the formation of an interface layer can be avoided, which ultimately allows ferroelectric memory to achieve unprecedented silicon-free 3D integration. The storage performance produced by this strategy cannot be achieved by conventional flash memory or previous perovskite ferroelectric memory. Device simulation confirmed that this strategy can achieve ultra-high density 3D memory integration.

Flash memory devices currently used in mass data storage for mobile devices and servers are based on floating gate or charge trap storage transistors that use electron tunneling through tunneling oxide (

,

). Since the electron tunneling process requires high-amplitude and long-duration voltage pulses, current flash memory devices usually require a high operating voltage of ~20 V and a slow speed of ~10

And show a limited endurance of about 10

cycle(

-

). In addition, it requires higher deposition temperature (>600°C) and/or annealing temperature (>900°C) to form the channel layer and oxide layer (

). In order to overcome these limitations, many types of emerging storage devices have been evaluated, but there are no substitutes for current flash memory (

). Ferroelectric memory transistors can replace current flash memory because it has the potential to run quickly at low power consumption (

). In a ferroelectric memory transistor, the charge in the channel layer can be directly controlled by the polarization of the ferroelectric layer, which is incorporated into the gate stack of the ferroelectric transistor (

). Although previous studies using ferroelectric perovskite oxide deposited on Si wafers have shown its feasibility as high-performance flash memory applications, the formation of an interface layer with Si channels will limit the storage window, durability and data retention characteristics (

). In addition, the complex composition of perovskite oxide limits the applicability of ferroelectric memory as next-generation flash memory devices (

). In addition, the three-dimensional (3D) integration of such ferroelectric memories is a key requirement for commercialization, but since depositing perovskite oxides and precious metals in a 3D structure is a difficult task, and these materials are very difficult to etch, this Is unachievable (

).

F-based ferroelectric materials have gained research interest due to their complementary metal oxide semiconductor (CMOS) compatibility, low power consumption and fast switching speed (

). In addition, recent studies have shown that while maintaining ferroelectricity, f-based ferroelectrics can be reduced to <1 nm (

). Due to these advantages, ha-based ferroelectric materials have been used in ferroelectric memory transistors, negative capacitance field effect transistors (FET), ferroelectric tunnel junctions and artificial synapses (

). F-based ferroelectric materials can be deposited conformally on vertical structures using atomic layer deposition (ALD), so ferroelectric transistors using them are considered useful for 3D memory (such as 3D NAND (

). However, it is still necessary to solve the device performance problem caused by the formation of the interface layer with Si channel (

Here, we propose a unique integration strategy to overcome the above-mentioned key problems in ferroelectric memory transistors by introducing indium zinc oxide (InZnO).

) As the semiconductor layer and zirconium-doped oxide ha (HfZrO

) As a ferroelectric layer. One, SiO

The use of InZnO can effectively prevent the interface layer inherent in traditional perovskite oxide or ferroelectric memory based on f oxide

As a semiconductor, while maintaining the necessary material quality (or material quality equivalent to Si) to obtain high-performance memory. This can increase the operating speed hundreds of times (<10

s), and the operating voltage (<5 V) is the current flash memory (

). In addition, since there is no interface layer, it has excellent durability (> 10

Ferroelectric transistor compared to two charge trap flash memory (~10 cycles)

) And ferroelectric transistors with Si channels (~10)

) (

). Since all processes can be completed at temperatures below 400°C, the integrated ferroelectric memory device is compatible with CMOS, so we can confirm that our process can achieve commercialization milestones, including demonstrations of NAND flash memory arrays and 3D vertical structures . Our nano-level 3D vertical flash memory has excellent performance and is expected to achieve ultra-high density 3D flash memory in the future. The 3D device displays a large storage window of 2.5 V and has 10 stable switching characteristics

cycle. Device simulation confirmed the operation mechanism and possibility of ultra-high-density 3D memory integration. These results prove the rationality of ALD-based ferroelectric memory as future 3D non-volatile storage devices (such as 3D vertical NAND).

Confirm the ferroelectric properties of HfZrO

, We made a capacitor with TiN/HfZrO

/ TiN structure and measure the polarization electric field (

-

) Characteristics of 24 nm thick HfZrO

(Figure S1A). Zirconia

Show positive residual polarization+

= 15.1μC/cm

And-the negative residual polarization-

= -13.8μC/cm

. Coercive electric field of HfZrO

It is ~1.2 MV/cm; it is larger than ferroelectric perovskite oxide (~0.05 MV/cm), and may be advantageous in ferroelectric transistors because a large coercive electric field leads to a large storage window (

). Therefore, using thin HfZrO can achieve a sufficient storage window

Compared with perovskite oxide. Ferroelectric of HfZrO

Piezoelectric force microscopy (PFM) and capacitance-voltage (

) Measurement. After applying -6 V to the outer square area of ​​the sample and then +6 V to the inner square area of ​​the sample, the PFM amplitude and phase image were measured. The obvious contrast difference indicates that the polarization state of HfZrO is different

In the PFM amplitude (Figure S1B) and phase image (Figure S1C). of

The ferroelectric properties of HfZrO cause the curve to show a butterfly lag

(Figure S1D). These results confirm the ferroelectric properties of HfZrO.

the film. Durability and polarization conversion characteristics of HfZrO

Be characterized. In order to obtain lasting characteristics, a repetitive voltage pulse with an amplitude of ±6 V and a width of 5 μs was applied (Figure S1E). Ferroelectric HfZrO

Demonstrates stable 10 switching characteristics

cycle. Polarization conversion characteristics of HfZrO

The light absorption rate was evaluated by measuring the switching and non-switching polarization characteristics under applied voltage pulses with an amplitude of 7.2 V (ie 3 MV/cm) and different widths (Figure S1F). As the pulse width increases from 30 ns to 700 ns, the switching polarization of HfZrO

increase.

In order to study the feasibility of our integration strategy, a ferroelectric thin film transistor (FeTFT) with bottom contact structure was fabricated by combining ALD-based HfZrO

And InZnO

(

). Quantify its electrical characteristics by scanning the gate voltage

Between -5 and 5 V at source-drain voltage

They are 0.1, 0.05 and 0.01V respectively. FeTFT shows counterclockwise hysteresis, which is caused by the iron polarization switching in HfZrO

). Linear field effect mobility of InZnO

The channel in FeTFT is about 1.9 cm

V

s

Lower than InZnO

On SiO

Layer (~7.8 cm

). This difference seems to be due to the high dielectric constant of HfZrO

Layer, which can cause long-range scattering of phonons (

). By using a gate electrode layer with a high electron density, the remote scattering of such phonons can be reduced (

). In addition, the mobility of InZnO

By optimizing process parameters, such as doping and growth temperature, the channel can be further increased (

). In order to quantify the storage window of FeTFT, the device is programmed and erased by applying positive voltage (5 V, 10 ms) and negative voltage (-5 V, 10 ms)

pulse. After applying each pulse,

Sweep from 0 V to -5 V to verify the state of the device. Threshold voltage

Use linear extrapolation to extract programming state and erase state

). Memory window, this is

The number of programmed and erased states in FeTFT (> 2 V) is greater than previously reported FeTFT (0.5 to 1 V) with f-based ferroelectric materials and oxide semiconductors (

). Determining the switching characteristics of FeTFT based on HfZrO

,

Pulses with different amplitudes and widths were applied. Before measurement, erase FeTFT by applying negative voltage

Pulse (-5 V, 10 ms). Then, apply a pulse with a width of 1 μs and an amplitude of 3 to 5 V in 0.2 V increments. As the pulse amplitude increases,

The equipment has been changed (

). Using a pulse with an amplitude of 5 V can reach a storage window of ~2 V, which is approximately four times the pulse amplitude required by conventional flash memory (

).

A change was also observed when the pulse width was increased from 100 ns to 1 μs with an amplitude of 5 V (

). These switching characteristics may be the result of partial polarization switching of HfZrO

The layer can be controlled by applying pulse conditions (

). With a voltage pulse width of 500 ns, a storage window of ~1 V can be reached, which is about hundreds of times faster than the erasing operation of conventional flash memory with the same storage window (

). The storage window of the flash memory depends on the storage operation, such as multi-level data storage, and when a smaller storage window is required, the flash memory can be operated faster (

). However, compared with the ferroelectric memory introduced in this study, a higher program/erase voltage (

). Confirm the reliability of FeTFT based on HfZrO

, We studied the endurance performance using devices with different storage windows of 0.5 and 1.5 V. By applying triangular pulses (5 V, -7 V) and (6 V, -8 V) to obtain 0.5 and 1.5 V storage windows (

And figure. S2). Pulse widths of 500 ns and 1 μs are used for programming and erasing operations, respectively. After applying continuous programming and erasing pulses, confirm the device status by scanning

From 0 to -5V. When the memory window is 0.5 V, FeTFT uses ALD-based HfZrO

cycle. The robustness of FeTFT based on ALD seems to be derived from its metal-ferroelectric semiconductor structure without interface layer (

). When the silicon layer is used as a channel, SiO

An interface layer can be formed between the channel and the ferroelectric layer, so a ferroelectric transistor with a Si channel has a metal-ferroelectric insulator-semiconductor (MFIS) structure (

). When

If it is applied to MFIS structure, a lot of applied electric fields can be induced in SiO

The interface layer has a low dielectric constant compared with the ferroelectric layer. High electric field in SiO

The interface layer can cause the charge to tunnel across SiO

Interfacial layer and cause charge trapping in the ferroelectric layer; it reduces endurance characteristics (

). In our FeTFT, the formation of the interface layer can be suppressed by using oxide semiconductor channels. No interface layer will produce stable endurance characteristics. In addition, a comparison was made between this work and previous storage devices (such as charge trap storage, perovskite oxide-based ferroelectric transistors and oxide-based ferroelectric transistors) (Table S1) (

). Use of HfZrO

Compared with traditional charge trap memory and perovskite oxide-based ferroelectric transistors, its operating voltage is lower, its operating speed is faster, and its processing temperature is lower. In addition, by avoiding the formation of SiO

The interface layer has strong durability compared with charge trap memory and ferroelectric transistors.

(

) Schematic diagram of FeTFT using HfZrO

. (

) FeTFT transfer curve

= 0.1, 0.05 and 0.01V. (

)

The curve of FeTFT in erased and programmed state. Threshold voltage

Extract using linear extrapolation. Memory window is the difference between erased and programmed

FeTFT.

FeTFT is based on (

) Amplitude and (

) The width of the programming pulse. In operations with different pulse amplitudes, the pulse amplitude is increased from 3 V to 5 V, and the width is fixed at 1 μs. In operations with different pulse widths, the pulse width is increased from 100 ns to 1 μs, and the amplitude is fixed at 5 V. (

The endurance characteristic of FeTFT is 10

Use positive (5 V, 500 ns) and negative (-7 V, 1 μs) triangular pulses for programming and erasing operations.

The structure of a ferroelectric NAND (FeNAND) flash memory array is similar to that of a NAND flash memory device (Figure S3A). The difference lies in the type of storage unit. FeNAND uses ferroelectric transistors, while NAND flash memory uses conventional flash memory. In FeNAND, the page consists of ferroelectric transistor memory cells that share a word line (WL). The FeNAND string includes ferroelectric transistor memory cells connected in series. All FeNAND strings share one source line (SL). Each NAND string is connected to the bit line (BL) (

). We fabricate 4×4 FeNAND arrays by integrating FeTFT with ferroelectric HfZrO

Layer and InZnO

Channel layer (Figure S3B). The manufacturing process of FeNAND is compatible with CMOS and can be performed below 400°C. First, deposit TiN on SiO for WL

/ Si substrate and HfZrO

The deposited layer is used for the ferroelectric layer. Deposition of Mo layer and InZnO for BL/SL

Deposit the layer of the channel layer. ALD is used to deposit HfZrO

Floor. Annealing process of induced ferroelectric phase in HfZrO

InZnO is deposited at 400°C for coating

Floor. The processing temperature of FeNAND is lower than that of ferroelectric devices based on perovskite oxide (> 700°C) (

). Finally, an etching process is performed to open the contacts for WL. The 4×4 FeNAND array is made up of four WL (WL

;

= 0, 1, 2 and 3) and four NAND strings (

). Each NAND string is connected to BL (BL

= 0, 1, 2 and 3). All NAND strings are connected to the same SL. In this 4×4 FeNAND array, each of the 16 memory cells

Located at the intersection of WL

And the NAND string on BL

. This array is used to demonstrate the program operation of FeNAND. In the NAND structure, undesired programming may occur in the memory cell that shares the WL with the selected memory cell during the program operation; therefore, unnecessary programming may occur in the memory cell. This phenomenon is called program interference (

). In order to avoid program interference, a method of prohibiting program operation is used. for example,

with

Selected as programmed and programmed suppressor cells respectively. Before the programming operation, the FeTFT memory cells in the FeNAND array are erased by applying an erase pulse with an amplitude of.

= −5 V, and the width of WL is 10 ms

, While applying 0 V to BL and SL (

). Then, program

, The amplitude is

= 5 V and apply a width of 10 ms to the selected WL

And apply 0 V to BL

. Prohibited program

Shared WL

versus

,Prohibited programming pulse with amplitude

= 2.5 V, with a width of 30 ms applied to BL

And SL (

). The passing amplitude is

= 2.5 V and a width of 30 ms is applied to the unselected WL.

It will also interfere with the state of the storage unit. Therefore, the effect

Study traffic interference by increasing the amplitude

From 0.5 to 4V. in

> 3 V, passing interference occurs, so

A voltage with an amplitude of 2.5 V is used for program prohibition operation (Figure S4). After erasing and programming operations, confirm the state of the memory cell by applying WL voltage

Scan (0→-5 V) to the selected WL

. During these operations, only the storage unit

Can be programmed by the voltage difference between the gate and the channel layer (

). Otherwise, the program may be prohibited by the prohibited program operation in the prohibited program unit

. and

Applied to BL

And SL, the channel potential can be increased; the voltage difference between the gate and the channel can be reduced to

-

). program

Prevent by using the program to prohibit the operation method

= 2.5 V because of the polarization switching of HfZrO

Layer in

Be obstructed (

). These results show that the voltage difference between the gate and the channel is small enough to avoid incorrect gate programming.

. In order to study how the program prohibition pulse affects the program prohibition unit, the program prohibition pulses with different amplitudes are used to execute the program operation (Figure S5). The amplitude of the programming prohibition pulse is increased from 0 V to 2.5 V in 0.5V increments. Prohibition of programming behavior depends on the magnitude.

. in

<1 V, program not needed for storage unit

(Unwanted cell) happened. As amplitude

Added, storage unit program

Was suppressed (

). Prohibit program running

= 2.5 V can successfully prevent harmful programs; repeated programs and program prohibition operations confirm this (Figure S6). These results show that through the application

.

) Optical image of a 4×4 FeNAND flash memory array (left) and a NAND string containing programmed cells in the FeNAND flash memory array (

) And the cell (

) (Correct). (

) Equivalent circuit of FeNAND flash memory array and erase/program operation.

with

Represents programming, erasing, pass and prohibit voltage respectively. (

Curve

Storage unit and

Memory cell after erasing and programming operations. program

The program prohibits the operation to prevent the storage unit. Prohibited programming pulse with amplitude

= 2.5 V is used to prohibit the program from running. During the prohibition period,

The storage unit can be upgraded to

All 16 memory cells in the FeNAND array are operating normally. Confirm the state of the storage unit by measurement

Curve of programming state and erase state (

). Memory cells in

Curve after programming and erasing operations. The status of the device can be confirmed non-destructively by measuring the string current when reading the voltage

Apply to selected cells. For lossless read operations, the amplitude is

The Δε is selected within a range that does not cause the switching of the polarization state in the ferroelectric layer. During application

When the amplitude is -2 V, the state of the memory cell does not change. Therefore, to read the state of the selected memory cell,

= −2 V is applied to the selected WL, and the BL reads the voltage

Sweep from 0 to 0.5 V. Read current by measuring

In the structure of the memory cell, the polarization state of the ferroelectric layer in the selected memory cell was confirmed.

10 out of 16 memory cells in the 4×4 FeNAND array were measured in the programmed and erased states (Figure S7).

According to the memory status shows obvious differences (

). Demonstrated string-level and page-level NAND operations using FeNAND devices. Three different cases of NAND strings are used (all programmed cells, one erased cell and all other programmed cells and all erased cells) (

The length of the string is

= -2 V is applied to all WLs. When all memory cells are programmed, the NAND string is in the on state. However, when the string contains at least one erased cell, the NAND string is in the off state because all memory cells in a string are connected in series (

). These results confirm that NAND storage operations can be performed using FeTFT arrays.

16 memory cells in programming and erasing states. (

) Statistical distribution of read current

The number of 16 memory cells in programmed (blue) and erased (red) states. (

) NAND operation: all programmed cells (case 1), one erased cell and all other programmed cells (case 2) and all erased cells (case 3). (

In cases 1, 2 and 3, the number of NAND strings is one. When even a cell is erased, the off state is obtained.

In order to study the wafer-level uniformity of the device, we fabricated FeNAND arrays on 4-inch SiO

/ Si wafer (Figure S8A). The programming and erasing operations of nine memory cells from different locations on the wafer were measured (Figure S8B). The memory cell in the programming and erasing state

(Figure S8C). These results indicate that FeNAND manufactured using ALD can exhibit uniform electrical characteristics in wafer size. Use programming pulses with different amplitudes

Demonstrated the tuning characteristics of the memory cell in FeNAND (Figure S9A). First, erase the memory cell by applying an erase pulse (-5 V, 10 ms). Then, programming pulses with amplitudes of 3.3, 3.8, and 5 V are applied. As the programming pulse amplitude increases,

The curve moves in the negative direction. Memory cell display in FeNAND

Use programming pulses with different amplitudes to repeat cycles for four different states (Figure S9B).

In order to confirm the feasibility of FeTFT as a 3D storage device, we fabricated a vertical FeTFT array by sequentially depositing SiO2 with a thickness of 50 nm

Insulator and 100 nm thick TiN gate electrode (

). As HfZrO

Layer is deposited using ALD, both layers are conformally deposited (

). Here, we define FeTFT with the middle TiN gate electrode located between SiO

Intermediate TFT (m-TFT). The effective channel area of ​​m-TFT is 10μm

(Channel length/width, 100 nm / 100μm). Research the electrical characteristics of m-TFT through application

Scan to m-TFT gate

When applied = 1 V

The voltage to the unselected gate (ie top and bottom TiN) electrodes is 1 V

). Observed n-type transfer characteristics with counterclockwise hysteresis

A scan of -5→5→-5V is applied to the m-TFT gate electrode. The storage window of the vertical FeTFT is about 2.5V. This result shows that FeTFT can operate in a vertical stack structure with a channel length of 100 nm. Verify the switching characteristics of m-TFT by applying voltage pulses with different pulse widths and amplitudes (

). The pulse width required for the programming operation decreases as the voltage pulse amplitude increases. In order to confirm the reliability of m-TFT, the endurance performance was studied by applying positive (6 V, 1μs) and negative (-7 V, 1μs) triangular pulses as programming pulses and erase pulses (

). After applying continuous programming and erasing pulses, confirm the device status by scanning

From 0 to -3 Vm-TFT exhibits a stable switching characteristic of 10

cycle. In addition, similar anti-clockwise hysteresis transmission characteristics were observed in m-TFT devices with an effective channel area of ​​0.2 μm.

(Length/Width, 20 nm / 10μm). These results indicate that the manufacturing process using our integrated strategy is compatible with 3D structured devices with large storage windows and excellent durability characteristics.

) Manufacturing process flow of vertical FeTFT array. (

) Optical image of vertical FeTFT device array. S and D represent the source and drain respectively. (

) Scanning electron microscope image (false color) of the cross-section of the vertical FeTFT array. (

) The transmission curve of m-TFT has a counterclockwise hysteresis. To characterize,

Scanning is applied to the m-TFT gate electrode, and

Apply = 1V to unselected gate electrodes. (

The m-TFT device changes according to the program pulse amplitude and width. (

) The durability of m-TFT device is 10

Use positive (6 V, 1μs) and negative (−7 V, 1μs) triangle pulses for programming and erasing operations, respectively.

We use technical computer-aided design (TCAD) tools to simulate the vertical FeTFT array (

). Before performing FeTFT simulation, we first perform simulation

Characteristics of 24 nm thick HfZrO ferroelectric capacitor

And compare with the experimental results (Figure S10) (

). TiN is used for the top and bottom electrodes; saturation polarization, residual polarization, coercive electric field and Landau-Khalatnikov parameters of HfZrO

Is extracted from experimental data (

). Simulated

The hysteresis is similar to the experimental results, which shows that the TCAD tool can be used to correctly simulate the ferroelectric properties. Refer to the experimental results to determine the material and its thickness (

). Apply a positive pulse (5 V, 100μs) and a negative pulse (-5 V, 100μs) to the m-TFT gate electrode (that is, the selected cell) for programming and erasing operations, while applying

= 1 V to unselected gate electrode. Polarization in HfZrO

After programming and erasing operations, this layer has changed significantly (

). continued,

After programming and erasing operations, a scan voltage of −3.5 to 2 V is applied to the fabricated and simulated vertical FeTFT array (

). The experimental and simulation results show similar programming and erasing characteristics. The results confirm that the electrical characteristics and operation of FeTFT can be correctly simulated using TCAD tools.

) Simulate the device structure of a vertical FeTFT array (

) The material used for the simulation and its thickness. (

) Enlarged image of vertical FeTFT array. (

Simulation of polarization in HfZrO

The layer is in the programmed and erased state. For programming and erasing operations, voltage pulses (5 V, 100 μs) and (-5 V, 100 μs) are applied to the m-TFT gate respectively. Polarization in HfZrO

After programming and erasing operations, the layer can obviously be changed. (

) Experiments and simulations

The curve of m-TFT in programming and erasing state.

Evaluate the feasibility of FeTFT based on HfZrO

In the future 3D FeNAND, we simulated a single string containing 16 WL, a string selection line and a ground selection line (

). The single string of 3D FeNAND is manufactured using a gate last process, which is similar to a terabit cell array transistor (Figure S11) (

). First, the nitride and oxide layers are sequentially deposited on a p-type (100) Si substrate, in which the n-well, p-well and source are formed by implanting 10 phosphorus

cm

Boron 10

And 10 arsenic

, Respectively. Etch a channel hole with a radius of 80nm; deposit an oxide semiconductor channel with a thickness of 10 nm, and fill the channel hole with SiO

(Ie filling material). Etch the nitride layer and HfZrO with a thickness of 24 nm

Be deposited. Finally, TiN WL and Mo BL were deposited. In our proposed 3D FeNAND, TiN with a thickness of 30 nm and HfZrO with a thickness of 24 nm

InZnO 10nm thick

, And Mo are respectively used as WL, ferroelectric gate insulator, oxide semiconductor channel and BL, and the thickness of SiO

The spacer between adjacent WLs is 30 nm. In order to observe the operating characteristics of 3D FeNAND, block erase and program operations (

). First, by applying a voltage pulse (10 V, 10 μs) to the substrate, block erase all WLs. Then, WL

And WL

The cells are programmed sequentially by applying voltage pulses (4 V, 1 μs) to the selected WL. After WL programming

Cell, WL

Use the same method to program the cell. Polarization in HfZrO

After block erase and program operation, the layer has changed significantly. In addition, the polarization state in WL

No change after WL programming

; This result shows that adjacent cells did not cause significant interference. continued,

Scan voltage from -3 to 1 V completes WL

After block erase and program operation (

). of

Features of WL

After programming adjacent cells (ie WL

), and has obviously switched to the programming state after WL programming

. In addition, a 3D FeNAND with more stacked cells was simulated using TCAD tools. The number of stacked batteries is 32, 64, and 128 (Figure S12). The electrical characteristics of the 3D FeNAND were characterized using the same procedure and block erase operation method discussed above. Using the above voltage pulse, all 3D FeNAND has been successfully programmed and erased, and the storage window is not significantly affected by the number of stacked cells, which confirms that 3D FeNAND can operate in a highly stacked structure. These results show that the proposed 3D FeNAND composed of low-power and fast-running FeTFT can replace 3D NAND flash memory.

) Simulate 3D FeNAND device structure. The simulation contains a single string of 16 WL, ground selection line (GSL) and string selection line (SSL). 30nm thick TiN, 24nm thick HfZrO

And 10 nm thick InZnO

Respectively used as WL, ferroelectric gate insulator and oxide semiconductor channel. Silica

Used as oxide filling material. SiO thickness

The interval between adjacent WLs is 30 nm. (

The second layer after block erase and programming operations. First, erase all WLs through a block erase operation. Then, WL

The cell is programmed. Finally, WL

The cell has been programmed. Polarization in HfZrO

After the block erase and program operations, the layer can obviously be changed. (

) Polarization changes after block erase and program operations. au, arbitrary unit. (

Curve in WL

After cell erase and programming operations.

We showed the combination of ferroelectric HfZrO

The oxide semiconductor channel is a unique integration strategy to solve the key problems in ferroelectric memory transistors. The device is manufactured using a CMOS compatible process at a lower processing temperature (400°C) and has a faster operating speed (<10

s), low operating voltage (<5 V) and excellent durability (> 10

Cycle), which is achieved through the synergy of ferroelectric HfZrO

Oxide semiconductor. We also studied the potential of ferroelectric memory as an alternative to conventional flash memory using integrated FeNAND and vertical FeTFT arrays. In FeNAND, program interference can be minimized by using the method of prohibiting program operation. In the prohibiting programming operation, the polarization switching of the ferroelectric layer is prevented by reducing the voltage difference between the gate and the channel. The state of the memory cells in the NAND string is successfully confirmed by a non-destructive read operation. of

The Pb of the FeTFT memory cell used for erasing and programming shows distinguishable programming and erasing states. In addition, a FeNAND array was used to demonstrate string-level and page-level NAND operations. Only the stored character string with all programmed cells is displayed in the on state; when even one cell is erased, the character string is displayed in the off state. A vertical FeTFT array is made by vertically stacking TiN gate electrodes and SiO2

Insulating layer to study its feasibility for 3D FeNAND. We verified that FeTFTs can operate in a vertical structure, and confirmed the operating mechanism through device simulation. Finally, by simulating programs and block erase operations in 3D FeNAND cells, the possibility of ultra-high density 3D memory integration was confirmed. These results indicate that FeTFT based on ALD has potential in future high-density 3D memory applications.

Hf [N(C

H

CH

]

[Tetra(ethylmethylamino) ha(TEMAH)] and Zr [N(C

[Tetra(ethylmethylamino)zirconium (TEMAZ)] was purchased from Korea UP Chemical. C

National Bureau of Statistics

in

[Bis(trimethylsilyl)amiyl diethyl indium (INCA-1)] and Zn(C

)

[Diethyl Zinc (DEZ)] was purchased from iChems, Korea. Si wafer with 100 nm thick thermally grown SiO

Used as a base.

Device fabricated on SiO

/ Si substrate. Use a mask aligner (MA6, Suss MicroTec) for photolithography. The FeNAND array is manufactured by integrating FeTFT. First, use DC sputtering to deposit TiN on SiO

The Si substrate is used as the gate electrode of FeTFT and as the WL of FeNAND. The TiN layer is patterned using a lift-off method. Then, use HfZrO with a thickness of 24 nm

Film is deposited on TiN/SiO

/ Si through alternating HfO ALD cycles

ZrO

Use TEMAH, TEMAZ and O at 280°C

Respectively as Hf precursor, Zr precursor and oxygen source. Electron beam evaporation is used to deposit Mo, as the source/drain electrodes of FeTFT and SL/BL of FeNAND. The Mo layer was patterned using a lift-off method. 20nm thick InZnO layer

Use INCA-1, DEZ and O to deposit films at 150°C

Respectively as indium precursor, zinc precursor and oxygen source. Zinc oxide

The layer is patterned using a combination of photolithography and wet etching. The channel length and width are 10 and 50 μm, respectively. Then, the device was thermally annealed under N at 400°C for 10 minutes

surroundings. The etching process is completed to open the contacts of the WL. For vertical FeTFT arrays, TiN with a thickness of 100 nm and SiO with a thickness of 50 nm

The layers are deposited sequentially using sputtering and plasma enhanced chemical vapor deposition, respectively. Titanium Nitride/Silica

/Titanium Nitride/Silica

Etching/TiN layer by dry etching (NE-7800, ULVAC) using sulfur hexafluoride (SF)

)plasma. 24 nm thick HfZrO

Layer, InZnO with a thickness of 20 nm

The channel layer and Mo source/drain electrodes were deposited using the same method as described above.

All electrical properties are measured under ambient conditions and room temperature. A semiconductor parameter analyzer (4200A-SCS, Keithley Instruments) was used to obtain electrical characteristics. Measure the ferroelectric properties after 10 applications

The period of rectangular bipolar pulse (±7.2 V, 5μs) is used to wake up HfZrO

(Figure S1). of

Use a pulse measurement unit (4225-PMU, Keithley Instruments) to measure the curve. A scanning probe microscope system (NX10, Park Systems) was used to obtain PFM images. To perform PFM measurements, a cantilever with a Pt-coated conductive tip was used to apply voltage to the sample and ground the bottom electrode. Polarize an area of ​​2.5 μm by 2.5 μm (outer square area) by applying -6 V at a scan rate of 0.5 Hz; then, apply a voltage of 6 V at a scan rate of 0.5 Hz to 1.5 μm × 1.5 μm (inner square area) ) To scan. After that, a reading process was performed on an area of ​​3 μm by 3 μm to verify the polarization state. of

Use impedance analyzer (4194A, HP) to measure the curve. Use an optical microscope (LV100ND, Nikon) to capture the optical image of the device. A high-resolution field emission scanning electron microscope (JSM-7800F PRIME, JEOL) was used to obtain a cross-sectional image of the device. The simulation was carried out using Sentaurus TCAD (Synopsys Inc.) software.

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It provides a unique three-dimensional integration strategy for high-performance, ultra-high-density ferroelectric memory.

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